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Espressif Systems /ESP32-C6 /PCR /RMT_SCLK_CONF

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Interpret as RMT_SCLK_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SCLK_DIV_A0SCLK_DIV_B0SCLK_DIV_NUM0SCLK_SEL 0 (SCLK_EN)SCLK_EN

Description

RMT_SCLK configuration register

Fields

SCLK_DIV_A

The denominator of the frequency divider factor of the rmt function clock.
SCLK_DIV_B

The numerator of the frequency divider factor of the rmt function clock.
SCLK_DIV_NUM

The integral part of the frequency divider factor of the rmt function clock.
SCLK_SEL

set this field to select clock-source. 0: do not select anyone clock, 1(default): 80MHz, 2: FOSC, 3: XTAL.
SCLK_EN

Set 1 to enable rmt function clock

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd